|
 |
Design Environment WG Activities
Activity of Design Environment Working Group
Those who have interest, contact us, please!
Chief: Tadatoshi Ishii(InterDesign Technologies, Inc.)
Mail: ishii.tadatoshi@interdesigntech.co.jp
Sub Chief: Koichi Kondo(Toshiba)
Mail: koichi1.kondo@toshiba.co.jp
During the past years, more and more researchers and engineers of universities
and industry come to have interest in and to understand SpecC designing
technology. And it is lately published some actual application case by
users. We think that it is getting more important to study more toward
actual and practical application of SpecC technology. So we started to
study system level design tool from users point of view.
Outline of WG Activity (Scheduled)
From users point of view, participants will have discussions about design
environment of SpecC technology, and we would like to hear and summarize
request and requirement toward practical application of SpecC design technology.
We think that we would like to have the discussion on the followings.
1) SpecC design technology and upper-level design environment (linkage
with UML and other SW design methodology)
2) Tools of SpecC design technology (SCE of UCI)
3) SpecC design technology and lower-level design environment (Tool chain
and linkage with logic synthesis tool and RTOS)
Activity(planned)
1) Evaluation on lower-level design environment
Some of STOC members have developed "SpecC-HDL Converter' - SpecC
- Verilog /HDL (RTL base) automatic mutual converter with support from
Information - technology Promotion Agency, Japan(IPA). STOC will open
it to members of the WG first.
It is planned that the tool will be free and open source, but at first
it will be disclosed to the WG members as one of STOC activities, and
we hope the members to utilize.
Design Environment WG wants to have such discussion of the tool from various
point of viewsAon such as introduction and improvement of C-based
design, trial of new usage of tool, various experiment and evaluation,
possibility of the application of C-based language to RTL design, difference
of logic synthesis and utilization of RTL IP.
We also hope to have discussions about evaluation of tool itself and its
function, how to effectively use and improve.
2) Discussion about Linkage between UML Design Environment
and SpecC Design technology
We have a lot of discussion about design methodology of system level design.
And now we come to know we have issues between system level design and
existing RTL design. This Design Environment WG wants to have discussions
how to bridge the gap between them based on SpecC design methodology.
3) Present Activity
- Mail base discussion
- Periodical meeting of members
- Reporting and summary of activity on yearly base
- Publication at STOC booth of a exhibition
Recruitment of New member
We hope to have new members of Design Environment WG.
Those who have interese, please contact Mr.Ishii (ishii.tadatoshi@interdesigntech.co.jp)
We would like to have new members such as follows.
- who wants to evaluate it using design motifs.(Motif is not necessary to
disclose)
- who wants to check how it works combining with other tools.
- Who have interest in the tool.
New members are recommended to be a member of STOC (general member or academic
member)
|
Why not to use SpecC-HDL converter (RTL base)!
|
Design Environment WG want to have deep discussion by the distribution of
the tool to the members.
"SpecC-HDL Converter" a tool of automatic converter based on RTL
data between USpecC language and VHDL, SpecC language and Verilog-HDL, it
will be open on binary base to members of the WG.
Compiler and simulation engine of uSpecC language v2.0 are also pdisclosed
to the WG members.
Let's study how to use it with the WG
people
- The tool can generate from VHDL/Verilog to SpecC
RTL and from SpecC RTL to VHDL, Verilog-HDL. That means you can use HDL
with C-language only.
- By conversion of language, you can make system level simulation.
- Co-simulation is possible based on C-language.
- You can establish design environment base on new C-based language.
- The tool is scheduled to be open source and it will be applied to various
environment.
| Contact |
| To: SpecC Technology Open Consortium office |
E-mail: |
|
|
|
